1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a circuit and a method for testing a nonvolatile semiconductor memory apparatus.
2. Related Art
Among nonvolatile semiconductor memory apparatuses, a PCRAM (phase change random access memory) belongs to a next generation memory apparatus which has advantages of both a flash memory and a random access memory, that is, the non-volatility of the flash memory and the high speed of the random access memory. In the PCRAM, data is stored using the properties of a chalcogenide material which is changed between an amorphous phase and a crystalline phase by application of heat.
Referring to FIG. 1, a conventional nonvolatile semiconductor memory apparatus includes a sense amplifier 10, a data storage region 20, first, second, and third transistors P1, N1, and P2, respectively, and a pass gate PG1.
The sense amplifier 10 senses the voltage level of a sense amplifier input node node_SAI.
The first transistor P1 provides a pumping voltage VPPSA for sense amplifier to the sense amplifier input node node_SAI in a read operation.
The second transistor N1 couples a sub input/output node node_SIO with the sense amplifier input node node_SAI in the read operation.
The third transistor P2 couples the sub input/output node node_SIO and a sub input/output voltage pad VSIO in a test mode, such that a voltage can be forced from test equipment to the sub input/output node node_SIO.
The data storage region 20 stores the resistance value of a specified material which is changed between an amorphous phase and a crystalline phase by heat, as a data value.
The pass gate PG1 couples the data storage region 20 and the sub input/output node node_SIO in the read operation.
The nonvolatile semiconductor memory apparatus configured as mentioned above operates as described below in the read operation.
As the pass gate PG1 and the second transistor N1 are turned on, the sense amplifier input node node_SAI and the data storage region 20 are coupled with each other, and the pumping voltage VPPSA for sense amplifier is applied to the sense amplifier input node node_SAI.
The sense amplifier 10 senses and amplifies the voltage level of the sense amplifier input node node_SAI.
The nonvolatile semiconductor memory apparatus outputs the voltage level sensed and amplified by the sense amplifier 10, as a data value.
In a test, as the first transistor P1 is turned on, the pumping voltage VPPSA for sense amplifier is applied to the sense amplifier input node node_SAI, and as the second transistor N1 is turned on, the sense amplifier input node node_SAI and the sub input/output node node_SIO are coupled with each other. Also, as the pass gate PG1 is turned off, the data storage region 20 and the sub input/output node node_SIO are decoupled from each other. Further, as the third transistor P2 is turned on, the sub input/output node node_SIO and the sub input/output voltage pad VSIO are coupled with each other, and a voltage is forced to the sub input/output node node_SIO from the test equipment.
While changing the voltage level applied to the sub input/output voltage pad VSIO from the test equipment, whether the sense amplifier 10 can normally sense and amplify the voltage level of the sense amplifier input node node_SAI is tested.
In such a test, only whether the sense amplifier 10 operates normally with the voltage level applied from an outside changed is tested, and a voltage level that can be normally sensed and amplified by the sense amplifier 10 cannot be tested.